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  • Change Makefile variable value

    - by paulgray
    Is there a way to reassign Makefile variable value inside of the target body? What I am trying to do is to add some extra flags for debug compilation: %.erl: %.beam $(ERLC) $(ERLFLAGS) -o ebin $< test: clean debug_compile_flag compile compile_test debug_compile: $(ERLCFLAGS) += -DTEST So if I invoke test target I would like to clean up my environment, add some new flags (like -DTEST to the existing ones), compile the whole code once again (first sources, then test modules). I do not want to copy/paste the code for compiling with some new flags set since there is a lot of logic put here and there. Is there some easy way to redefine the variable value so I can reuse the existing code?

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  • How to generate a Makefile with source in sub-directories using just one makefile.

    - by James Dean
    I have source in a bunch of subdirectories like: src/widgets/apple.cpp src/widgets/knob.cpp src/tests/blend.cpp src/ui/flash.cpp In the root of the project I want to generate a single Makefile using a rule like: %.o: %.cpp $(CC) -c $< build/test.exe: build/widgets/apple.o build/widgets/knob.o build/tests/blend.o src/ui/flash.o $(LD) build/widgets/apple.o .... build/ui/flash.o -o build/test.exe When I try this it does not find a rule for build/widgets/apple.o. Can I change something so that the %.o: %.cpp is used when it needs to make build/widgets/apple.o ?

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  • Makefile option/rule to handle missing/removed source files

    - by b3nj1
    http://stackoverflow.com/questions/239004/need-a-makefile-dependency-rule-that-can-handle-missing-files gives some pointers on how to handle removed source files for generating .o files. I'm using gcc/g++, so adding the -MP option when generating dependencies works great for me, until I get to the link stage with my .a file... What about updating archives/libraries when input sources go away? This works OK for me, but is there a cleaner way (ie, something as straightforward as the g++ -MP option)? #BUILD_DIR is my target directory (includes Debug/Release and target arch) #SRC_OUTS are my .o files LIBATLS_HAS = $(shell nm ${BUILD_DIR}/libatls.a | grep ${BUILD_DIR} | sed -e 's/.*(//' -e 's/).*://') LIBATLS_REMOVE = $(filter-out $(notdir ${SRC_OUTS}), ${LIBATLS_HAS}) ${BUILD_DIR}/libatls.a: ${BUILD_DIR}/libatls.a(${SRC_OUTS}) ifneq ($(strip ${LIBATLS_REMOVE}),) $(AR) -d $@ ${LIBATLS_REMOVE} endif

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  • compiling lua, getting makefile CreateProcess error

    - by Iggyhopper
    I'm trying to compile Lua 1.1. Why? Because I can. Here's the makefile contents. all: (cd src; make) (cd clients/lib; make) (cd clients/lua; make) clean: (cd src; make clean) (cd clients/lib; make clean) (cd clients/lua; make clean) Here's the error I get just from running make all. (cd src; make) process_begin: CreateProcess((null), (cd src; make), ...) failed. make (e=2): The system cannot find the file specified. make: *** [all] Error 2 Why do I get this error? I'm on WinXP-32.

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  • Modifiers in Makefile rule's dependency list

    - by gnu_maker
    The problem is fairly simple. I am trying to write a rule, that given the name of the required file will be able to tailor its dependencies. Let's say I have two programs: calc_foo and calc_bar and they generate a file with output dependent on the parameter. My target would have a name 'target_*_*'; for example, 'target_foo_1' would be generated by running './calc_foo 1'. The question is, how to write a makefile that would generate outputs of the two programs for a range of parameters?

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  • Explaining makefile

    - by Michael
    xpi_built := $(build_dir)/$(install_rdf) \ $(build_dir)/$(chrome_manifest) \ $(chrome_jar_file) \ $(default_prefs) xpi_built_no_dir := $(subst $(build_dir)/,,$(xpi_built)) $(xpi_file): $(build_dir) $(xpi_built) @echo "Creating XPI file." cd $(build_dir); $(ZIP) ../$(xpi_file) $(xpi_built_no_dir) @echo "Creating XPI file. Done!" $(build_dir)/%: % cp -f $< $@ $(build_dir): @if [ ! -x $(build_dir) ]; \ then \ mkdir $(build_dir); \ fi can anyone explain me this makefile part? particularly interested in $(build_dir)/%: % as well as $< and $@ directives two labels $(build_dir) exists, I guess both are executed, but in which order?

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  • configure.in: AM_DISABLE_SHARED doesn't change my Makefile

    - by t2k32316
    I'm extremely new to using Makefiles and autoconf. I'm using the Camellia image library and trying to statically link my code against their libraries. When I run "make" on the Camellia image library, I get libCamellia.a, .so, .la, and .so.0.0.0 files inside my /usr/local/lib directory. This is the command I use to compile my code with their libraries: gcc -L/usr/local/lib -lCamellia -o myprogram myprogram.c This works fine, but when I try to statically link, this is what I get: gcc -static -L/usr/local/lib -lCamellia -o myprogram myprogram.c /tmp/cck0pw70.o: In function `main': myprogram.c:(.text+0x23): undefined reference to `camLoadPGM' myprogram.c:(.text+0x55): undefined reference to `camAllocateImage' myprogram.c:(.text+0x97): undefined reference to `camZoom2x' myprogram.c:(.text+0x104): undefined reference to `camSavePGM' collect2: ld returned 1 exit status I want to statically link because I'm trying to modify the Camellia source code and I want to compare my version against theirs. So after some googling, I tried adding AM_DISABLE_SHARED into the configure.in file. But after running ./configure, I still get the exact same Makefile. After I "make install", I still get the same results above. What is an easy way to get two versions of my code, one with the original Camellia source code compiled and one with my modified version? I think static libraries should work. There is an easy way to get static libraries working or are there other simple solutions to my problem? I just don't want to re-"make" and re-"make install" everytime I want to compare my version against the original.

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  • Makefile : Build in a separate directory tree

    - by Simone Margaritelli
    My project (an interpreted language) has a standard library composed by multiple files, each of them will be built into an .so dynamic library that the interpreter will load upon user request (with an import directive). Each source file is located into a subdirectory representing its "namespace", for instance : The build process has to create a "build" directory, then when each file is compiling has to create its namespace directory inside the "build" one, for instance, when compiling std/io/network/tcp.cc he run an mkdir command with mkdir -p build/std/io/network The Makefile snippet is : STDSRC=stdlib/std/hashing/md5.cc \ stdlib/std/hashing/crc32.cc \ stdlib/std/hashing/sha1.cc \ stdlib/std/hashing/sha2.cc \ stdlib/std/io/network/http.cc \ stdlib/std/io/network/tcp.cc \ stdlib/std/io/network/smtp.cc \ stdlib/std/io/file.cc \ stdlib/std/io/console.cc \ stdlib/std/io/xml.cc \ stdlib/std/type/reflection.cc \ stdlib/std/type/string.cc \ stdlib/std/type/matrix.cc \ stdlib/std/type/array.cc \ stdlib/std/type/map.cc \ stdlib/std/type/type.cc \ stdlib/std/type/binary.cc \ stdlib/std/encoding.cc \ stdlib/std/os/dll.cc \ stdlib/std/os/time.cc \ stdlib/std/os/threads.cc \ stdlib/std/os/process.cc \ stdlib/std/pcre.cc \ stdlib/std/math.cc STDOBJ=$(STDSRC:.cc=.so) all: stdlib stdlib: $(STDOBJ) .cc.so: mkdir -p `dirname $< | sed -e 's/stdlib/stdlib\/build/'` $(CXX) $< -o `dirname $< | sed -e 's/stdlib/stdlib\/build/'`/`basename $< .cc`.so $(CFLAGS) $(LDFLAGS) I have two questions : 1 - The problem is that the make command, i really don't know why, doesn't check if a file was modified and launch the build process on ALL the files no matter what, so if i need to build only one file, i have to build them all or use the command : make path/to/single/file.so Is there any way to solve this? 2 - Any way to do this in a "cleaner" way without have to distribute all the build directories with sources? Thanks

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  • Makefile trickery using VPATH and include.

    - by roe
    Hi, I'm playing around with make files and the VPATH variable. Basically, I'm grabbing source files from a few different places (specified by the VPATH), and compile them into the current directory using simply a list of .o-files that I want. So far so good, now I'm generating dependency information into a file called '.depend' and including that. Gnumake will attempt to use the rules defined so far to create the included file if it doesn't exist, so that's ok. Basically, my makefile looks like this. VPATH=A/source:B/source:C/source objects=first.o second.o third.o executable: $(objects) .depend: $(objects:.o=.c) $(CC) -MM $^ > $@ include .depend Now for the real question, can I suppress the generation of the .depend file in any way? I'm currently working in a clearcase environment - sloooow, so I'd prefer to have it a bit more under control when to update the dependency information. It's more or less an academic exercise as I could just wrap the thing in a script which is touching the .depend file before executing make (thus making it more recent than any source file), but it'd interesting to know if I can somehow suppress it using 'pure' make. I cannot remove the dependency to the source files (i.e. using simply .depend:), as I'm depending on the $^ variable to do the VPATH resolution for me. If there'd be any way to only update dependencies as a result of updated #include directives, that'd be even better of course.. But I'm not holding my breath for that one.. :)

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  • GNU Makefile book

    - by Michael
    Any books you would recommend to learn scripting makefiles? I know gnu.org has manual, but hope there is a book with better explanations and examples.

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  • makefile: how to call macros in macros

    - by Matthias Günther
    Hello, I have the following macros in my make file: pdf: // do something clean: // just another fancy thing No I want to declare a macro all: which include (or call) the makros above. The following thing doesn't work: all: pdf: clean: I don't want to repeat the code from pdf: and clean: in order not to rebel against DRY principle. Thanks for your help.

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  • Makefile : contains string

    - by Michael
    The variable returns MINGW32_NT-5.1 or CYGWIN_NT-5.1. (yea, dot at the end) Need to compare that given var contains NT-5.1 positioned anywhere. Using cygwin and would like to be compatible with pretty much any *nix.

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  • How to use external makefile in Eclipse

    - by Morpheus
    Hi all! I have a source code of an OpenSource project which I get from SVN. I was able to run autogen -- configure -- and make successfully (through the terminal). But I want to build the same project with Eclipse, and I can't port manually those source files to eclipse though. So, How can I set Eclipse to use external make files ? can anyone please help me ? Thanks.

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  • VPATH in makefile issue.

    - by Ashok Patil
    Hello, I have a question related to VPATH. I'm playing around with make files and the VPATH variable. Basically, I'm grabbing source files from a few different places (specified by the VPATH), and trying to compile them into the another directory ( $CURDIR/OBJ/ ) using simply a list of .o-files that I want. Can I create .o's in any another directory other than current dir when using VPATH??

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  • Makefile : assigning function variable in target command line

    - by Michael
    I need the xpi_hash variable to be assigned only when update target's command is decided to execute. Then I'm using this variable as environment, exporting, etc.. If I put it outside of rule, it will be expanded firstly, before $(xpi) target is called, hence will not find that file. update: $(xpi) $(target_update_rdf) xpi_hash := $(shell sha1sum $(xpi) | grep -Eow '^[^ ]+') @echo "Updating..." and above of course is not correct, because for command part the shell is represented. So maybe another way to put this question is - how to bring variable as command output?

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  • Makefile generic pattern rule -- xyzzy-en_US.ext2 from xyzzy.ext0

    - by Janne Savukoski
    I can't figure out a way to define a generic pattern rule for the following kind of production with make: require xyzzy-en_US.ext2 from xyzzy.ext0 via xyzzy.ext1. This works: all: xyzzy-en_US.ext2 # to be compiled from xyzzy.ext0 %.ext1 : %.ext0 # produce xyzzy.ext1 %-en_US.ext2 : %.ext1 # produce xyzzy-en_US.ext2 But how to generalize the locale part of the second rule? Or do I need to generate rules for all different locales? Neither of these work: %-??_??.ext2 : %.ext1 # ... %.ext2 : $(@,%-??_??.ext2,%.ext1) # ...

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  • Makefile variable initialization and export

    - by Michael
    somevar := apple export somevar update := $(shell echo "v=$$somevar") all: @echo $(update) I was hoping to apple as output of command, however it's empty, which makes me think export and := variable expansion taking place on different phases. how to overcome this?

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  • Problem with makefile

    - by sterh
    Hello. I created a python project in IDE Anjuta, added some python files and the problem follows. I need that would make the program after a few .py files lying in src copied to dir /usr/bin. Anjuta generates enormous configure- and makefiles. 'll Show you need to register and where that would make described above. Thank you.

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  • Makefile patsubs double replacement

    - by aaa
    hello. is a possible to do something like this, without shell command: CXX_MODULES += $(patsubst %, %/%.cpp, $(LIBRARIES)) notice double replacement which does not work (only first replacement happens) after some tinkering I came up with $(join $(LIBRARIES), $(patsubst %, /%.cpp, $(LIBRARIES))) Thank you

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  • What is wrong in this simple Makefile

    - by Walidix
    SRC_VAR = test string for variable manipulation. TEST1_VAR = $(subset for,foo,${SRC_VAR}) all: @echo original str: ${SRC_VAR} @echo substitution: ${TEST1_VAR} This is the output: original str: test string for variable manipulation. substitution: The output should be: original str: My test string for variable manipulation. substitution: My test string foo variable manipulation.

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