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  • Compile OpenSSL from source using Xilinx EDK

    - by Asanka
    I want to use openSSL functions in my xilinx C++ project. So i downloaded the source and tried to compile using the makefile. But unfortunately the linux box I was provided did not contained the required software (perl5, make, etc) to compile the source using makefile. So as the second option i tried to compile the source as a shared library. So i made a new project using existing openSSL source. But all the attempts were failed since it gave lots of errors including missing headers, unknown defines etc. If someone knows how to compile openssl as a shared library using Xilinx toolchains please help me. It would be really helpful if someone can provide the complete project which can be opened using Xilinx EDK. If better alternative exists to use openssl with xilinx toolchains please explain that also. Thanks in advance....

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  • How to define clock input in Xilinx

    - by seventeen
    Hey, I have almost no experience with Xilinx. I have a group project for a Digital Logic course that is due soon, where my partner, who was supposed to take care of the Xilinx simulations decided to bail on me. So here I am trying to figure it out last minute. I have designed a synchronous counter using a few JK Flip Flops and I need to define the CLK input for the FJKCs. I have drawn up the correct schematic, but I cannot figure out how to define a clock input. Any help appreciated, and yes, this is homework. I just can't find any basic xilinx documentation/tutorials online and I honestly don't have time to learn the whole IDE.

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  • Looking for library declaration of IP Module

    - by Martin
    Hi, I want to use the Xilinx hardware module of the ICAP controller in my own design. This module uses the following library: library hwicap_v5_00_a; use hwicap_v5_00_a.all; I was looking in the directories as well as subdirectories of Xilinx\12.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores but I could not find the package declaration of hwicap. Anyone an idea where Xilinx "hides" this information. Many thanks

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  • Question regarding XST bitstream generation

    - by Richi
    Hi all, I have a very simple VHDL module, consisting of a few lines of code. The thing is, when I generate the bitstream, I end up with a huge bitstream. The reason for this is, I guess, that XST adds lots of extra information so that the bitstream can run standalone on a FPGA. However, for my purpose it would be interesting to see the size of the bitstream of the module alone without any extra bits and pieces, just the vaniall module alone. Is there an option in Xilinx ISE 12.1 that allows me to do that? Many thanks, Richi

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  • Verilog errors during synthesis

    - by chester.boo
    Here is the code in question: http://pastebin.com/smqUNpdt When I do a syntax check, everything is okay. But when I try to synthesize with XST I get the following errors: ERROR:Xst:870 - "fibonacci.v" line 42: Can not simplify operator DIV. ERROR:Xst:899 - "fibonacci.v" line 29: The logic for <out> does not match a known FF or Latch template. ERROR:Xst:899 - "fibonacci.v" line 30: The logic for <ratio> does not match a known FF or Latch template. ERROR:Xst:899 - "fibonacci.v" line 36: The logic for <nextstate> does not match a known FF or Latch template. ERROR:Xst:899 - "fibonacci.v" line 37: The logic for <previousstate> does not match a known FF or Latch template. ERROR:Xst:899 - "fibonacci.v" line 38: The logic for <presentstate> does not match a known FF or Latch template. ERROR:Xst:899 - "fibonacci.v" line 39: The logic for <fib_number_cnt> does not match a known FF or Latch template.

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  • Modelsim (XE III/Starter 6.4b) not allowing me to define a macro function

    - by montooner
    I'm working on a Xiling FPGA for a course project. Normally we use the lab computers, but I'm trying to install on my own computer. So, I'm trying to include a macro file using line: `include "Const.v" But the following macro function doesn't work. Any ideas why? `ifdef synthesis // if Synplify `define SYNPLIFY `define SYNTHESIS `define MACROSAFE `else // if not Synplify `ifdef MODELSIM `define SIMULATION `define MACROSAFE `else `define XST // synthesis translate_off // if XST then stop compiling `undef XST `define SIMULATION `define MODELSIM // synthesis translate_on // if XST then resume compiling `ifdef XST `define SYNTHESIS `define MACROSAFE `endif `endif `endif //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Section: Log2 Macro // Desc: A macro to take the log base 2 of any number. Useful for // calculating bitwidths. Warning, this actually calculates // log2(x-1), not log2(x). //------------------------------------------------------------------------------ `ifdef MACROSAFE `define log2(x) ((((x) > 1) ? 1 : 0) + \ (((x) > 2) ? 1 : 0) + \ (((x) > 4) ? 1 : 0) + \ (((x) > 8) ? 1 : 0) + \ (((x) > 16) ? 1 : 0) + \ (((x) > 32) ? 1 : 0) + \ (((x) > 64) ? 1 : 0) + \ (((x) > 128) ? 1 : 0) + \ (((x) > 256) ? 1 : 0) + \ (((x) > 512) ? 1 : 0) + \ (((x) > 1024) ? 1 : 0) + \ (((x) > 2048) ? 1 : 0) + \ (((x) > 4096) ? 1 : 0) + \ (((x) > 8192) ? 1 : 0) + \ (((x) > 16384) ? 1 : 0) + \ (((x) > 32768) ? 1 : 0) + \ (((x) > 65536) ? 1 : 0) + \ (((x) > 131072) ? 1 : 0) + \ (((x) > 262144) ? 1 : 0) + \ (((x) > 524288) ? 1 : 0) + \ (((x) > 1048576) ? 1 : 0) + \ (((x) > 2097152) ? 1 : 0) + \ (((x) > 4194304) ? 1 : 0) + \ (((x) > 8388608) ? 1 : 0) + \ (((x) > 16777216) ? 1 : 0) + \ (((x) > 33554432) ? 1 : 0) + \ (((x) > 67108864) ? 1 : 0) + \ (((x) > 134217728) ? 1 : 0) + \ (((x) > 268435456) ? 1 : 0) + \ (((x) > 536870912) ? 1 : 0) + \ (((x) > 1073741824) ? 1 : 0)) `endif

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  • kernel panic with exitcode=0x00000004 and no call trace

    - by litmusconfig
    A bit of background first - I'm trying to configure a MicroBlaze Linux (big-endian version) system on a Xilinx ML506 eval board. The goal is to use the second partition of a CompactFlash card attached to the Xilinx SystemACE controller. So far, root in initramfs works and after boot, I can mount and use said partition, no problem. But if I try to use it right from the getgo with the "root=/dev/xsa2" kernel command line parameter, the system hangs with [...] Freeing unused kernel memory: 143k freed Kernel panic - not syncing: Attempted to kill init! exitcode=0x00000004 And that's it - no regdump, no call trace, no further nothing from the serial console, even though kernel has been configured with debugging enabled. Now, I'm pretty new at this, so is there something else I should be doing to see something more informative from the kernel?

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  • How to generate `AllowDeactivateGrabs` in command line ?

    - by boffin
    I am using XFCE-Ubuntu and do a lot of my development work there. In my case, when I sometimes use Xilinx ISE, the mouse cursor hangs as a Grab pointer and then stops responding. The entire X environment becomes unusable and I have to kill it and restart. This is becoming a serious annoyance. I saw this bug: AllowDeactivateGrabs is broken I see that sending AllowDeactivateGrabs in command line can kill the Grab. In my case, I am doing this on a remote server, so it is the application in the remote server (over X2GO) getting messed up. I am able to login in command line and kill X. Is there a way to generate AllowDeactivateGrabs in command line ? So I dont mess up my other applications and potentially lose data.

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  • Should you remove all warnings in your Verilog or VHDL design? Wh or why not?

    - by Brian Carlton
    In (regular) software I have worked at companies where the gcc option -Wall is used to show all warnings. Then they need to be dealt with. With non-trivial FPGA/ASIC design in Verilog or VHDL there are often many many warnings. Should I worry about all of them? Do you have any specific techniques to suggest? My flow is mainly for FPGAs (Altera and Xilinx in particular), but I assume the same rules would apply to ASIC design, possibly more so due to the inability to change the design after it is built.

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  • Should you remove all warnings in your Verilog or VHDL design? Why or why not?

    - by Brian Carlton
    In (regular) software I have worked at companies where the gcc option -Wall is used to show all warnings. Then they need to be dealt with. With non-trivial FPGA/ASIC design in Verilog or VHDL there are often many many warnings. Should I worry about all of them? Do you have any specific techniques to suggest? My flow is mainly for FPGAs (Altera and Xilinx in particular), but I assume the same rules would apply to ASIC design, possibly more so due to the inability to change the design after it is built.

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  • Running lmgrd on ubuntu 14.04 LTS

    - by SumanBhatR
    I have installed Xilinx 14.7 in ubuntu 14.04 LTS machine(i386 - 64bit). But I am unable to run lmgrd (for starting the license server). When I googled this problem, I found that lsb-core package needs to be installed. But the package is having many dependencies, I want to know how to install lsb-core package with all the necessary dependencies. Thanks for the help On running sudo apt-get install lsb-core I got the following output Reading package lists... Done Building dependency tree Reading state information... Done Package lsb-core is not available, but is referred to by another package. This may mean that the package is missing, has been obsoleted, or is only available from another source E: Package 'lsb-core' has no installation candidate So I downloaded lsb-core package from http://packages.ubuntu.com/trusty/misc/lsb-core site and used "sudo dpkg -i ./lsb-core_4.1+Debian11ubuntu6_i386.deb" to install it By doing it, I got the following output Selecting previously unselected package lsb-core. (Reading database ... 163205 files and directories currently installed.) Preparing to unpack .../lsb-core_4.1+Debian11ubuntu6_i386.deb ... Unpacking lsb-core (4.1+Debian11ubuntu6) ... dpkg: dependency problems prevent configuration of lsb-core: lsb-core depends on libc6 ( 2.3.5). lsb-core depends on libz1. lsb-core depends on libncurses5. lsb-core depends on libpam0g. lsb-core depends on lsb-invalid-mta (= 4.1+Debian11ubuntu6) | mail-transport-agent. lsb-core depends on at. lsb-core depends on binutils. lsb-core depends on cron | cron-daemon. lsb-core depends on libc6-dev | libc-dev. lsb-core depends on locales. lsb-core depends on m4. lsb-core depends on mailx | mailutils. lsb-core depends on ncurses-term. lsb-core depends on pax. lsb-core depends on psmisc. lsb-core depends on alien (= 8.36). lsb-core depends on python3. lsb-core depends on lsb-security (= 4.1+Debian11ubuntu6). lsb-core depends on time. dpkg: error processing package lsb-core (--install): dependency problems - leaving unconfigured Processing triggers for man-db (2.6.7.1-1) ... Errors were encountered while processing: lsb-core So I want to know how to install lsb-core package with all the necessary dependencies in one go. Thanks for the help

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  • Chroot into a 32 bit version of ubuntu from a 64 bit host

    - by Leif Andersen
    I have a piece of software that only runs on 32 bit linux (Xilinx webPack 10.1, apperently it 'has' to be the old version because that's the latest one compatible with their boards), anyway, this version is only compatible with 32 bit linux. So, I head off to this page to see what I can do: https://help.ubuntu.com/community/32bit_and_64bit Of the 4 options (listed at the bottom): I already installed ia32-libs, and it's still not working I could do that one if needed (which I ended up doing). No, I don't want to be working from a vm all of next semester, that would be painful and I'd rather just reinstall my whole computer to a 32 bit os (which I don't want to do). It didn't sound like it was the best option based on what I've seen. So I went off to do #2, and set up a chroot for 32 bit ubuntu. It linked to this tutorial: https://help.ubuntu.com/community/DebootstrapChroot As I'm running ubuntu 10.10 I made the lucid and newer version changes. Which is to say I wrote: [hardy-i386] description=Ubuntu 8.04 Hardy for i386 directory=/srv/chroot/hardy-i386 personality=linux32 root-users=leif type=directory users=leif to /etc/schroot/chroot.d/hardy-i386 (Note though that I did save it once before I had the file properly formatted, I saved the correct version moments later though). I then ran: $ sudo mkdir -p /srv/chroot/hardy_i386 $ sudo debootstrap --variant=buildd --arch i386 hardy /srv/chroot/hardy_i386 http://archive.ubuntu.com/ubuntu/ Then I ran: $ schroot -l And it showed the proper chroot, but then when I ran: $ schroot -c hardy-i386 -u root I got the following error: E: 10mount: error: Directory '/srv/chroot/hardy-i386' does not exist E: 10mount: warning: Mount location /var/lib/schroot/mount/hardy-i386-80359697-2164-4b10-a05a-89b0f497c4f1 no longer exists; skipping unmount E: hardy-i386-80359697-2164-4b10-a05a-89b0f497c4f1: Chroot setup failed: stage=setup-start Can anyone help me figure out what the problem is? Oh, by the way: /srv/chroot/hardy-i386 most certainly exists. I've also tried it replacing all references with hardy to lucid, to no avail. Oh, one more thing, I did set up the chrome os environment a month back or so: http://www.chromium.org/chromium-os/developer-guide and it had me use something with chmod. So, can anyone figure out what the problem is? Thank you.

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  • Why is wget so much faster than Firefox at some downloads?

    - by Earlz
    Recently, I needed to do an update of Xilinx WebPack, mind you, this is one hefty piece of software. It weighs in at 6gigs, which definitely isn't "quick" on any internet I've ever had available to me. So, when I went to download it(using Firefox of course), I was very... unsettled by the fact that the download was only going at 110kByte/s. My internet connection is capable of about 2200kByte/s download, so what gives!? My workaround in the past for this issue has been to take the link to my Linode linux server and download it there with wget, where the download will zip along at 14MByte/s, and then either copying it to my website directory and downloading it that way through HTTP, or using sftp. Both ways work about as well and will sufficiently max out my connection. However, I recently figured out the missing variable. I tried doing the download locally with wget and was able to max out my connection! TL;DR; Now, my question. Why is wget so much faster than firefox at downloading this file? I hardly ever have such a difference in download speeds except for with this one file.

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  • Multidimensional array problem in VHDL?

    - by Nektarios
    I'm trying to use a multidimensional array in VHDL and I'm having a lot of trouble getting it to work properly. My issue is that I've got an array of 17, of 16 vectors, of a given size. What I want to do is create 17 registers that are array of 16 * std_logic_vector of 32 bits (which = my b, 512). So, I'm trying to pass in something to input and output on the register instantiation that tells the compiler/synthesizer that I want to pass in something that is 512 bits worth... Similar to in C if I had: int var[COLS][ROWS][ELEMENTS]; memcpy(&var[3].. // I'm talking about 3rd COL here, passing in memory that is ROWS*ELEMENTS long (My actual declaration is here:) type partial_pipeline_registers_type is array (0 to 16, 0 to 15) of std_logic_vector(iw - 1 downto 0); signal h_blk_pipelined_input : partial_pipeline_registers_type; I tried simply using h_blk_pipelined_input(0) .. up to (16) but this doesn't work. I get the following error, which makes me see that I need to double index in to the array: ERROR:HDLParsers:821 - (at the register) Wrong index type for h_blk_pipelined_input. So then I tried what's below, and I get this error: ERROR:HDLParsers:164 - (at the register code). parse error, unexpected TO, expecting COMMA or CLOSEPAR instantiate_h_pipelined_reg : regn generic map ( N=> b, init => bzeros ) port map ( clk => clk , rst => '0', en => '1', input => h_blk_pipelined_input((i - 1), 0 to 15), output=> h_blk_pipelined_input((i), 0 to 15)); -- Changing 0 to 15 to (0 to 15) has no effect... I'm using XST, and from their documentation (http://www.xilinx.com/itp/xilinx6/books/data/docs/xst/xst0067_9.html), the above should have worked: ...declaration: subtype MATRIX15 is array(4 downto 0, 2 downto 0) of STD_LOGIC_VECTOR (7 downto 0); A multi-dimensional array signal or variable can be completely used: Just a slice of one row can be specified: MATRIX15 (4,4 downto 1) <= TAB_B (3 downto 0); One alternative is that I can create more registers that are 16 times smaller, and instead of trying to do all '0 to 15' at once, I would just do that 15 additional times. However, I think this may lead to inefficiency in synthesis and I don't feel like this is the right solution. EDIT: Tried what Ben said, instantiate_h_m_qa_pipeline_registers: for i in 1 to 16 generate instantiate_h_pipelined_reg : regn generic map ( N=> b, init => bzeros ) port map ( clk => clk , rst => '0', en => '1', input => h_blk_pipelined_input(i - 1), output=> h_blk_pipelined_input(i)); end generate instantiate_h_m_qa_pipeline_registers; The signals are now defined as: type std_logic_block is array (0 to 15) of std_logic_vector(iw - 1 downto 0) ; type partial_pipeline_registers_type is array (0 to 16) of std_logic_block; signal h_blk_pipelined_input : partial_pipeline_registers_type; And the error I get from XST is: ERROR:HDLParsers:800 - ((where the register part is)) Type of input is incompatible with type of h_blk_pipelined_input. I'm able to do everything I was able to do before, using ()() syntax instead of ( , ) so I haven't lost anything going this way, but it still doesn't resolve my problem.

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