I am trying to make 24 wires in total very quickly but I keep getting the error:

Error (10170): Verilog HDL syntax error at your_ALU_mux.v(81) near text "="; expecting ".", or an identifier

Here is my code:

module your_ALU_mux(your_out, operandA, operandB, opcode, switches, address);
input [7:0] operandA, operandB, address;
input [3:0] opcode, switches;
output [7:0] your_out;

wire [0:7] Bnot, newb, newa;
wire Cin, Cout;

    not
       (Bnot[0], operandB[0]),
       (Bnot[1], operandB[1]),
       (Bnot[2], operandB[2]),
       (Bnot[3], operandB[3]),
       (Bnot[4], operandB[4]),
       (Bnot[5], operandB[5]),
       (Bnot[6], operandB[6]),
       (Bnot[7], operandB[7]);

// Getting A' and B'
    if (address == 16'h00 || address == 16'h01)
    // Add A + B
    if (address == 16'h00)

        // newa = A
        newa[0] = operandA[0];
        newa[1] = operandA[1];
        newa[2] = operandA[2];
        newa[3] = operandA[3];
        newa[4] = operandA[4];
        newa[5] = operandA[5];
        newa[6] = operandA[6];
        newa[7] = operandA[7];

        // newb = B'
        newb[0] = Bnot[0];
        newb[1] = Bnot[1];
        newb[2] = Bnot[2];
        newb[3] = Bnot[3];
        newb[4] = Bnot[4];
        newb[5] = Bnot[5];
        newb[6] = Bnot[6];
        newb[7] = Bnot[7];

        // Carry in = 1
        Cin = 1;


        // A-B
    else if (address == 16'h01)
        // newb = B
        newb[0] = operandB[0];
        newb[1] = operandB[1];
        newb[2] = operandB[2];
        newb[3] = operandB[3];
        newb[4] = operandB[4];
        newb[5] = operandB[5];
        newb[6] = operandB[6];
        newb[7] = operandB[7];

        // newa = A
        newa[0] = operandA[0];
        newa[1] = operandA[1];
        newa[2] = operandA[2];
        newa[3] = operandA[3];
        newa[4] = operandA[4];
        newa[5] = operandA[5];
        newa[6] = operandA[6];
        newa[7] = operandA[7];

        // Carry in = 0
        Cin = 0;



end
        RippleCarryAdd A+B(.S0(your_out[0]), .S1(your_out[1],.S2(your_out[2],.S3(your_out[3],.S4(your_out[4],.S5(your_out[5]
                                    S6.(your_out[6]), S7.(your_out[7],
                                    .Cout(Cout),.Cin(Cin),
                                    .A0(newa[0]),.A1(newa[1]),.A2(newa[2]),.A3(newa[3]),.A4(newa[4]),.A5(newa[5]),
                                    .A6(newa[6]),.A7(newa[7]),
                                    .B0(newb[0]),.B1(newb[1]),.B2(newb[2]),.B3(newb[3]),.B4(newb[4]),
                                    .B5(newb[5]),.B6(newb[6]),.B7(newb[7]));

endmodule

I also get in error saying:

Error (10170): Verilog HDL syntax error at your_ALU_mux.v(66) near text "if"; expecting "endmodule"

And the it brings me to my first if statement.

Is this the wrong way of going about creating wires and them using them?