Question regarding XST bitstream generation

Posted by Richi on Stack Overflow See other posts from Stack Overflow or by Richi
Published on 2011-02-28T14:33:40Z Indexed on 2011/02/28 15:24 UTC
Read the original article Hit count: 324

Filed under:

vhdl

|

xilinx

Hi all,

I have a very simple VHDL module, consisting of a few lines of code. The thing is, when I generate the bitstream, I end up with a huge bitstream. The reason for this is, I guess, that XST adds lots of extra information so that the bitstream can run standalone on a FPGA.

However, for my purpose it would be interesting to see the size of the bitstream of the module alone without any extra bits and pieces, just the vaniall module alone. Is there an option in Xilinx ISE 12.1 that allows me to do that?

Many thanks, Richi

© Stack Overflow or respective owner

Related posts about vhdl

Case statements in VHDL

as seen on Stack Overflow - Search for 'Stack Overflow'
Hi, When programming in VHDL, can you use a variable in a case statement? This variable will modified by one of the cases i.e. case task is when 1 => when 2 => when number => is this OK? >>> More
error when synthesizing VHDL code

as seen on Stack Overflow - Search for 'Stack Overflow'
I am getting the warning that: One or more signals are missing in the sensitivity list of always block. always@(Address)begin ReadData = instructMem[Address]; end How do I get rid of this warning? >>> More
include floating point library in vhdl

as seen on Stack Overflow - Search for 'Stack Overflow'
I have pex_pkg.vhd and I want to use this library to make floating point adder but altera max+plus II give me an error can't open "PEX_lib" how to include this library in max+plus ? >>> More
VHDL, using arithmetic & variables in "downto"?

as seen on Stack Overflow - Search for 'Stack Overflow'
Hey, Quick VHDL question, I don't have access to Xilinx at the moment due to dead laptop, so can't test this. I was wondering if it's possible to use variables and arithmetic in 'downto' statements, e.g: proc: process (x) begin y <= z(x downto 0) & z(7 downto x); end process; Thanks. >>> More
VHDL - Problem with std_logic_vector

as seen on Stack Overflow - Search for 'Stack Overflow'
Hi, i'm coding a 4-bit binary adder with accumulator: library ieee; use ieee.std_logic_1164.all; entity binadder is port(n,clk,sh:in bit; x,y:inout std_logic_vector(3 downto 0); co:inout bit; done:out bit); end binadder; architecture binadder of binadder is signal state:… >>> More

Related posts about xilinx

Compile OpenSSL from source using Xilinx EDK

as seen on Stack Overflow - Search for 'Stack Overflow'
I want to use openSSL functions in my xilinx C++ project. So i downloaded the source and tried to compile using the makefile. But unfortunately the linux box I was provided did not contained the required software (perl5, make, etc) to compile the source using makefile. So as the second option i tried… >>> More
How to define clock input in Xilinx

as seen on Stack Overflow - Search for 'Stack Overflow'
Hey, I have almost no experience with Xilinx. I have a group project for a Digital Logic course that is due soon, where my partner, who was supposed to take care of the Xilinx simulations decided to bail on me. So here I am trying to figure it out last minute. I have designed a synchronous counter… >>> More
Looking for library declaration of IP Module

as seen on Stack Overflow - Search for 'Stack Overflow'
Hi, I want to use the Xilinx hardware module of the ICAP controller in my own design. This module uses the following library: library hwicap_v5_00_a; use hwicap_v5_00_a.all; I was looking in the directories as well as subdirectories of Xilinx\12.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores but… >>> More
Verilog errors during synthesis

as seen on Stack Overflow - Search for 'Stack Overflow'
Here is the code in question: http://pastebin.com/smqUNpdt When I do a syntax check, everything is okay. But when I try to synthesize with XST I get the following errors: ERROR:Xst:870 - "fibonacci.v" line 42: Can not simplify operator DIV. ERROR:Xst:899 - "fibonacci.v" line 29: The logic for <out>… >>> More
Verilog code simulates but does not run as predicted on FPGA

as seen on Stack Overflow - Search for 'Stack Overflow'
I did a behavioral simulation of my code, and it works perfectly. The results are as predicted. When I synthesize my code and upload it to a spartan 3e FPGA and try to analyze using chipscope, the results are not even close to what I would have expected. What have I done incorrectly? http://pastebin… >>> More