Question regarding XST bitstream generation

Posted by Richi on Stack Overflow See other posts from Stack Overflow or by Richi
Published on 2011-02-28T14:33:40Z Indexed on 2011/02/28 15:24 UTC
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Hi all,

I have a very simple VHDL module, consisting of a few lines of code. The thing is, when I generate the bitstream, I end up with a huge bitstream. The reason for this is, I guess, that XST adds lots of extra information so that the bitstream can run standalone on a FPGA.

However, for my purpose it would be interesting to see the size of the bitstream of the module alone without any extra bits and pieces, just the vaniall module alone. Is there an option in Xilinx ISE 12.1 that allows me to do that?

Many thanks, Richi

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