output not updating until next clock cycle

Posted by EquinoX on Stack Overflow See other posts from Stack Overflow or by EquinoX
Published on 2010-05-04T21:57:37Z Indexed on 2010/05/04 22:18 UTC
Read the original article Hit count: 278

Filed under:

verilog

|

vhdl

|

system-verilog

I have the code module below

always @(posedge Clk) begin

ForwardA = 0;
ForwardB = 0;

//EX Hazard
if (EXMEMRegWrite == 1) begin
 if (EXMEMrd != 0)
    if (EXMEMrd == IDEXrs)
        ForwardA = 2'b10;
   if (EXMEMrd == IDEXrt && IDEXTest == 0)
        ForwardB = 2'b10;
end


//MEM Hazard

if (MEMWBRegWrite == 1) begin
 if (MEMWBrd != 0) begin
    if (!(EXMEMRegWrite == 1 && EXMEMrd != 0 && (EXMEMrd == IDEXrs)))
            if (MEMWBrd == IDEXrs)
                ForwardA = 2'b01;
    if (IDEXTest == 0) begin
        if (!(EXMEMRegWrite == 1 && EXMEMrd != 0 && (EXMEMrd == IDEXrt)))
            if (MEMWBrd == IDEXrt)
                ForwardB = 2'b01;
    end
 end
end

end

The problem is that the output, which is ForwardA and ForwardB is not updated not on the rising clock edge rather than on the next rising clock edge... why is this?? How do I resolve so that the output is updated on the same positive rising clock edge?

Here's what I mean: alt text

ForwardA is updated with 2 on the next rising clock edge and not on the same rising clock edge

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